1. Field of the Invention
The present invention relates to an access time measurement of a Pseudo SRAM (PSRAM), and more particularly, to a self refresh circuit for measuring a real access time of the PSRAM, that is, the access time of a refresh operation that is performed during a memory access operation in the PSRAM.
2. Description of the Related Art
Static Random Access Memory (SRAM) is widely used in the field of high-speed data transmission and mobile devices. Because the price per capacity of SRAM is relatively high, SRAM is inappropriate for large-capacity memory systems. Accordingly, a demand for Pseudo SRAM (PSRAM) is increasing, centering on mobile devices. While PSRAM uses internally dynamic memory cells rather than static cells, it operates much the same like an SRAM.
From a standpoint that the PSRAM device internally employs dynamic memory cells, the PSRAM is also referred to as Uni-transistor RAM (UtRAM). In a Dynamic RAM (DRAM), which uses the dynamic memory cell consisting of a cell capacitor and a cell transistor for switching the cell capacitor, a leakage current may be generated due to the inherent characteristics of the dynamic memory cell. Therefore, written data must be refreshed at regular periodic intervals. Meanwhile, because the PSRAM processes the refresh operation of the DRAM internally, an external circuit such as a memory controller needs not be involved in the refresh operation of the PSRAM device. Thus, the PSRAM can operate much the same as an SRAM.
The PSRAM has advantages in terms of large capacity and low cost. However, compared with the SRAM using the static cell, low power consumption and high operating speed have been raised as important requirements for the PSRAM.
The PSRAM has a lower operation speed than that of the SRAM because it performs the refresh operation internally. Specifically, in the PSRAM, an elapsed time from input of a command to output of data can vary depending on whether a refresh operation is being performed during a read operation or a write operation. For example, access time when the refresh operation is performed during the read operation is longer than an access time when the refresh operation is not performed during the read operation.
FIG. 1 is a block diagram of a conventional self refresh circuit of a PSRAM. The block diagram illustrated in FIG. 1 is an example of the self refresh circuit that can process the internal self refresh of the PSRAM.
Referring to FIG. 1, the conventional refresh circuit 100 includes an internal refresh oscillator 101, a refresh control signal generator 110, a refresh command generator 120, a word line (WL) control pulse generator 130, and an internal refresh circuit 150.
The internal refresh oscillator 101 generates a refresh period pulse SRFH at a constant period according to inherent refresh characteristics of the semiconductor memory device, for example, the refresh period and the refresh cycle. Accordingly, the internal refresh oscillator 101 can be configured with an oscillator and the like.
The refresh control signal generator 110 receives the refresh period pulse SRFH from the internal refresh oscillator 101 and generates a refresh control signal SRFHP. Also, the refresh control signal generator 110 receives a self-refresh-entrance inhibiting signal NERFH from the WL control pulse generator 130. When the self-refresh-entrance inhibiting signal NERFH is activated, entrance into the self refresh operation is interrupted.
Accordingly, based on the self-refresh-entrance inhibiting signal NERFH and the refresh period pulse SRFH, the refresh control signal generator 110 activates the refresh control signal SRFHP to a logic ‘LOW’ when the refresh period pulse SRFH precedes the self-refresh-entrance inhibiting signal NERFH. When the self-refresh-entrance inhibiting signal NERFH precedes the refresh period pulse SRFH, the refresh control signal generator 110 delays the activation of the refresh control signal SRFHP until the read or write operation is completed.
As described above, the WL control pulse generator 130 generates the self-refresh-entrance inhibiting signal NERFH based on a logical combination of a pulse output from an Address Transition Detector (ATD; not shown) and other signals.
The refresh command generator 120 generates a refresh command pulse RFHTD, which instructs the internal refresh circuit 150 to execute the refresh operation, when the refresh control signal SRFHP is activated.
The internal refresh circuit 150 may include an address counter, a WL selector and other suitable elements for performing the refresh operation. The address counter operates in response to the refresh command pulse RFHTD, and the WL selector selects a word line to be refreshed.
Because the self-refresh-entrance inhibiting signal NERFH and the refresh period pulse SRFH are not synchronized with each other, as described above, priority of the two signals is arbitrary and may vary in different embodiments. Therefore, an elapsed time from the input of a command to the output of data is flexibly changed depending on whether the refresh operation is performed during the read operation or the write operation of the memory cell array.
FIGS. 2A and 2B are timing diagrams illustrating signal flow in the PSRAM.
FIG. 2A is a timing diagram of a signal flow when the refresh operation is not performed during the read operation in the PSRAM.
An ATD pulse PPT is generated at the ATD in response to an external input of an address, and a dummy pulse PUL_RD0 is generated in response to the ATD output pulse PPT.
Referring to FIG. 2A, the output of the refresh control signal SRFHP is delayed because the self-refresh-entrance inhibiting signal NERFH is activated earlier than the refresh period pulse SRFH.
Accordingly, when the ATD again generates an internal ATD signal RATD at a point in time when a section of the dummy pulse PUL_RD0 is finished, the read operation on the memory is immediately performed to output data DOUT.
FIG. 2B is a timing diagram of a signal flow when the refresh operation is performed during the read operation in PSRAM.
The dummy pulse PUL_RD0 is generated in response to the ATD output pulse PPT that is output from the ATD based on the external input of the address as described in FIG. 2A.
Referring to FIG. 2B, the self refresh operation is performed prior to the read operation because the refresh period pulse SRFH is activated earlier than the self-refresh-entrance inhibiting signal NERFH. Namely, the refresh control signal SRFHP is activated by the refresh period pulse SRFH and the refresh command RFHTD is generated by the activation of the refresh control signal SRFHP, so that the internal refresh circuit 150 performs the refresh operation.
Unlike the case of FIG. 2A in which the read operation is performed immediately following with completion of the dummy pulse PUL_RD0, in this case, the read operation is performed when the ATD generates the internal ATD signal RATD again at point in time when the section of the dummy pulse PUL_RD0 is finished and the self refresh operation is completed in FIG. 2B.
As described in FIGS. 2A and 2B, the PSRAM of FIGS. 2A and 2B have different access times for the cases where the refresh operation is not performed during a read operation (FIG. 2A) and where the refresh operation is performed during a read operation (FIG. 2B).
In terms of product specifications such as the AC characteristic that represent the performance of the product, an access time from a column address (hereinafter, referred to as a tAA) in the case where the refresh is involved has significant meaning. The tAA in the case where the refresh is involved is defined as a real tAA. Specifically, in testing the product, the real tAA measurement is important in terms of screening speed.
According to the conventional devices, the greatest tAA, which is measured while a timing of a command is shifted incrementally in the test operation, is considered as the real tAA.
Thus, the real tAA is measured by repeating several times the input of the command and through a trial-and-error method using a skewed timing. This type of measurement is inappropriate for a correct tAA measurement, and also causes time loss in the product test.